This invention relates to phase and frequency modulation and more particularly to apparatus and methods for precise phase and frequency modulation of phase-locked loop frequency synthesizers.
It is known in the art that a phase-locked loop circuit can be angle modulated (phase of frequency modulated) over a wide band of frequencies that includes frequencies both greater than and less than the loop bandwidth by injecting modulation components at two separate circuit nodes of the phase-locked loop system. For example, U.S. Pat. No. 4,052,672, issued to Enderby et al. discloses a programmable divide-by-N phase-locked loop system wherein frequency modulation is effected over a relatively wide range of modulation frequencies by phase modulating the system via a first modulation path for all frequencies within the loop bandwidth and by frequency modulating the loop via a second modulation path for all modulating frequencies outside the loop bandwidth. More specifically, in such a prior art arrangement, the first modulation path includes circuitry for integrating the applied modulation signal and for summing the integrated signal with the signal provided by the phase-locked loop phase detector. The second modulation path includes circuitry for summing the applied modulation signal with the frequency control signal (i.e., the loop error signal) that is coupled to the phase-lock loop voltage-controlled oscillator (VCO). Relatively flat modulation characteristics are achieved in such a system by establishing the gain constant (i.e., sensitivity) of the modulation path that includes the integrator circuit substantially equal to the reciprocal of the loop bandwidth.
An alternative prior art arrangement frequency modulates the phase-locked loop reference oscillator, rather than phase-modulating the system phase detector. More specifically, such a prior arrangement differs from the above-described system in that the integrator circuit is omitted and the first modulation path controls the frequency of a reference oscillator (e.g., a voltage-controlled crystal oscillator) that provides the reference signal to the phase-locked loop phase detector. In such a system relatively flat modulation will be attained as long as the gain factor associated with the path including the voltage-controlled crystal oscillator is established so that product of the frequency deviation of the reference oscillator, multiplied by frequency division ratio (N) of the phase-locked loop is equal to the deviation produced by the voltage controlled oscillator that supplies the system output signal.
Although prior art systems of the above-mentioned types may provide satisfactory operation under some conditions, disadvantages and drawbacks are encountered when the phase-lock loop is configured to provide carrier frequencies over an extended frequency range (e.g., an octave or more) and when additional circuitry is included within the phase-lock loop. In particular, the frequency division ratio, N, in such a system is not a constant, but is varied to select the desired carrier frequency. Moreover, the gain factor of the system VCO (K.sub.v) is not constant, but exhibits a somewhat unpredictable variation with frequency unless, for example, specialized circuit arrangements such as a YIG-tuned voltage-controlled oscillator are employed. With respect to the inclusion of additional circuitry within the phase-lock loop, such circuitry is often required in order to provide additional features or effect operation beyond the capabilities of a basic phase-lock loop. For example, the copending patent application of Floyd D. Erps, entitled PHASE-LOCK LOOP FREQUENCY SYNTHESIZER, filed of even date with this appliction and assigned to the assignee of this invention discloses a programmable divide-by-N phase-lock loop which provides frequency resolution greatly exceeding that of conventionally-arranged phase-locked loops wherein some embodiments of the disclosed system include a complete phase-locked loop that is embedded in the feedback path of the frequency synthesizer loop. This additional phase-locked loop, in effect, serves as a tracking filter which attenuates spurious signal components produced by a single-sideband mixer circuit.
The high resolution phase-locked loop system disclosed in the above-mentioned patent application of Floyd Erps, and other phase-locked loop arrangements that have additional frequency sensitive networks in the loop feedback path do not exhibit flat modulation characteristics when modulated by the previously-discussed prior art techniques. Further, the variation in the frequency division ratio that is required in order to provide the desired carrier frequencies and frequency-related deviations in the gain factor of the VCO of a phase-locked loop system can easily prevent a system from attaining a desired modulation flatness, including the high resolution phase-locked loop system disclosed in the above-mentioned patent application of Erps.
Accordingly, it is an object of this invention to provide a circuit arrangement for angle modulation of a phase-locked loop system which is augmented with frequency-sensitive components or networks that are embedded in the phase-locked loop feedback path.
It is another object of this invention to provide a signal source that can be selectively phase or frequency modulated wherein the signal source includes compensation for carrier frequency-related variations in the gain factors associated with the loop VCO and compensation for changes in the loop frequency division ratio as well as compensation for variations caused by frequency-sensitive networks that are embedded in the phase-locked loop feedback path.
Still further, it is an object of this invention to provide a modulation compensation network for a high resolution phase-locked loop system of the type disclosed in the above-referenced patent application of Floyd D. Erps.